🔌 E1 Multiplexer Study Guide

Operation, Buffers, Processor & Memory Architecture
For Digital Communication Undergraduate Students

📚 Learning Objectives

🎯 Primary Goals

  • Understand E1 frame structure and multiplexing principles
  • Analyze buffer management and synchronization
  • Study processor architecture for TDM control
  • Examine memory organization and addressing

🔧 Technical Skills

  • Calculate bit rates and time slot allocation
  • Analyze jitter and wander in buffers
  • Design memory mapping schemes
  • Evaluate processor timing requirements

📊 Standards

  • ITU-T G.703/G.704 - Physical/Electrical characteristics
  • ITU-T G.706 - Frame structure
  • ITU-T G.732 - Primary PCM multiplex equipment

🌐 E1 System Overview

E1 (European Standard): A digital transmission link operating at 2.048 Mbps, carrying 32 time slots (30 for voice/data, 2 for signaling/sync) in a Time Division Multiplexing (TDM) frame structure.

Key Specifications

Parameter Value Description
Bit Rate 2.048 Mbps Total transmission rate
Time Slots 32 (TS0-TS31) 8 bits each = 256 bits/frame
Frame Duration 125 μs 8000 frames/second
Voice Channels 30 TS1-TS15, TS17-TS31
Signaling TS16 CAS (Channel Associated Signaling)
Synchronization TS0 Frame alignment word

E1 Frame Structure Visualization

Basic E1 Frame (256 bits, 125μs)

TS0
FAS
TS16
SIG

Red = Frame Alignment Teal = Signaling Blue = Voice/Data

💾 Buffer Architecture

1. Elastic Store Buffers (Slip Buffers)

Purpose: Compensate for phase and frequency differences between incoming tributary streams and the local multiplex clock. Essential for plesiochronous operation.
Write Clock (Input)

fin ≈ 2.048 MHz ± 50 ppm

→
Elastic Buffer (FIFO)
Center Fill = 50%

Typical Size: 2-8 frames (512-2048 bits)

→
Read Clock (Output)

fout = 2.048 MHz (System Clock)

Buffer Operation Modes

🟢 Normal Operation

Fill level maintained at 50% ± 25%. Continuous read/write with no slips.

Threshold High: 75% → Slow read
Threshold Low: 25% → Fast read

🟡 Controlled Slip

When buffer overflows or underflows, entire frames are repeated or deleted.

Slip Rate < 1 frame/day
ITU-T G.822 specification

🔴 Frame Slip

Loss of frame alignment causes major slips. System re-synchronizes.

Frame Loss: 1/8000 s = 125μs
Max slips: 5 in 24 hours

2. Frame Alignment Buffer

Function: Stores incoming bits until the Frame Alignment Signal (FAS) is detected in TS0. Required for demultiplexing to identify frame boundaries.
Input Stream
FAS Detect
Aligned Out

3. Jitter Attenuation Buffer

Reduces high-frequency phase variations (jitter) from the incoming signal:

🖥️ Processor Architecture

Multiplexer Control Processor

Role: Manages time slot assignment, signaling extraction/insertion, alarm monitoring, and interface control. Typically an embedded microcontroller or DSP.
📥
Input
Interface
→
⚡
Time Slot
Interchange
→
🔧
Signaling
Processor
→
📤
Output
Interface

Processor Functional Blocks

▶ Frame Processor Unit (FPU)
  • Frame Alignment: Searches for FAS pattern (0011011) in TS0
  • CRC-4 Generation/Check: Error detection for TS0 (bits 1-4)
  • Remote Alarm Indication: Monitors bit 3 of TS0 for AIS
  • Timing: Generates 8kHz frame pulse, 2.048MHz bit clock
FAS Pattern: 0 0 1 1 0 1 1 (7 bits)
Frame Clock: 8000 Hz (125μs period)
Multiframe: 16 frames (2ms)
▶ Time Slot Interchanger (TSI)

The TSI allows any input time slot to be switched to any output time slot:

  • Control Memory: Stores connection map (32 entries × 5 bits)
  • Data Memory: Double-buffered RAM for concurrent read/write
  • Speed: Must complete read-modify-write in 3.9μs (1/256 of frame)
Parameter Value
Switching Capacity 32 × 32 non-blocking
Connection Setup Time < 125μs (1 frame)
Control Memory Access Every 3.9μs (256 accesses/frame)
▶ Signaling Processor

Handles Channel Associated Signaling (CAS) in TS16:

  • Multiframe Alignment: Detects MFAS (0000) in Frame 0, TS16
  • ABCD Bits: Extracts signaling bits for each channel (2 per frame, 4 total)
  • Signaling Map: Maintains state for 30 channels × 4 bits = 120 bits
16-Frame Multiframe Structure: Frames 0-15, where Frame 0 contains MFAS (0000) in TS16 bits 1-4, and Frames 1-15 carry ABCD signaling for channels 1-15 and 17-31.
▶ Alarm & Maintenance Processor

Monitors line quality and generates alarms:

  • LOS (Loss of Signal): No transitions for 10-255 bit periods
  • LOF (Loss of Frame): 2-5 consecutive incorrect FAS
  • AIS (Alarm Indication Signal): All ones in TS0
  • RAI (Remote Alarm Indication): Bit 3 of TS0 = 1

🗂️ Memory Organization

Memory Architecture Overview

E1 Multiplexer Memory Map (Typical 8KB System)

CR0
CR1
CR2
CR3
CR4
CR5
CR6
CR7
SR0
SR1
SR2
SR3
SR4
SR5
SR6
SR7
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
S0
S1
S2
S3
S4
S5
S6
S7
S8
S9
S10
S11
S12
S13
S14
S15
B0
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
B13
B14
B15
Control/Status TSI/Signaling Data Buffers

Memory Types and Functions

🎮 Control Registers (CR)

Size: 8-16 bytes
Access: Processor read/write
Function:

  • Enable/disable channels
  • Set loopback modes
  • Configure clock sources
  • Interrupt enables

📊 Status Registers (SR)

Size: 8-16 bytes
Access: Processor read-only (hardware set)
Function:

  • Real-time alarm status
  • Error counters (CRC, framing)
  • Slip event counts
  • Interrupt flags

🔄 TSI Control Memory

Size: 32 × 8 bits = 32 bytes
Access: Dual-port (CPU + hardware)
Function:

  • Input-to-output time slot map
  • Connection table
  • Broadcast/multicast config

📞 Signaling Memory

Size: 16 × 8 bits = 16 bytes
Access: Updated every 2ms (multiframe)
Function:

  • ABCD bits for 30 channels
  • Multiframe alignment
  • Signaling change detection

💾 Data Buffer RAM

Size: 2-8 KB
Access: DMA by frame processor
Function:

  • Elastic storage (2-8 frames)
  • Frame alignment buffer
  • Jitter attenuation

⚙️ Program Memory

Size: 4-32 KB (ROM/Flash)
Access: Processor fetch
Function:

  • Firmware for control processor
  • Configuration tables
  • Alarm handling routines

Memory Timing Calculations

Critical Timing Requirements:

1. Frame Period: Tframe = 125 μs
2. Bit Period: Tbit = 1/2.048MHz = 488 ns
3. Time Slot Period: Tts = 8 × Tbit = 3.9 μs

Memory Bandwidth Calculation:
- Data Memory: 256 bits/frame × 8000 frames/s = 2.048 Mbps
- Control Memory: 32 accesses × 8 bits × 8000 = 2.048 Mbps
- Total Bandwidth: ~4.1 Mbps (minimum)

Access Time Requirement:
- Must complete one access every 3.9 μs (time slot period)
- RAM speed required: < 500 ns (for dual-port implementation)

⚙️ Operational Procedures

1. Initialization Sequence

  1. Hardware Reset: Clear all registers, reset FIFO pointers
  2. Clock Configuration: Select master/slave mode, set PLL parameters
  3. Memory Init: Clear buffers, set TSI to straight-through (TSn→TSn)
  4. Frame Alignment: Enable FAS search, wait for synchronization
  5. Channel Enable: Turn on voice channels (TS1-15, TS17-31)
  6. Interrupt Enable: Unmask alarms and slip events

2. Normal Operation Flow

Frame Pulse
Buffer Write
TSI Access
Buffer Read

3. Slip Handling Procedure

Slip Detection: Buffer fill level crosses threshold (High: >75%, Low: <25%)
Condition Action Effect
Buffer Overflow (>75%) Skip read pointer ahead by 1 frame Loss of 256 bits (32 bytes)
Buffer Underflow (<25%) Repeat previous frame (read pointer hold) Duplication of 256 bits
Frame Loss Enter hunt mode, search for FAS Service interruption ~1-2 ms

🧮 Interactive Calculators

Buffer Size Calculator

50 ppm
24 hours
Calculating...

Memory Bandwidth Calculator

Calculating...

📋 Summary & Key Takeaways

🔑 Key Concepts

  • E1 uses TDM with 32 time slots at 2.048 Mbps
  • Elastic buffers compensate for clock differences
  • Frame alignment uses FAS pattern in TS0
  • TSI enables flexible time slot switching
  • Signaling carried in TS16 (CAS)

⚠️ Critical Design Factors

  • Buffer size vs. slip rate trade-off
  • Memory bandwidth for real-time operation
  • Processor speed for frame processing
  • Jitter tolerance in clock recovery
  • Alarm detection and handling latency

🎓 Study Checklist

© 2026 Digital Communications Study Guide | E1 Multiplexer Architecture

Based on ITU-T G.703, G.704, G.706, and G.732 standards