T1 PDH Virtual Laboratory

Explore the Plesiochronous Digital Hierarchy T1 system (1.544 Mbps). Learn frame structure, line coding (AMI/B8ZS), and time-division multiplexing through interactive simulations.

1 Learning Objectives

Understand the T1 frame structure: 24 time slots × 8 bits + 1 framing bit = 193 bits at 8000 frames/second

Analyze AMI (Alternate Mark Inversion) line coding and its polarity alternation scheme

Examine B8ZS (Binary 8 Zero Substitution) for maintaining clock synchronization

Compare D4 Super Frame (SF) and Extended Super Frame (ESF) formats

Understand DS0 channel multiplexing (64 kbps per channel, 56 kbps with signaling)

Calculate bit rate: (24 × 8 + 1) × 8000 = 1.544 Mbps

2 Theory

T1 Frame Structure

The T1 carrier is the North American standard for digital transmission, operating at 1.544 Mbps. It multiplexes 24 voice channels (DS0s) using Time Division Multiplexing (TDM).

F
24 × 8-bit Time Slots
193 bits total (1 framing bit + 192 data bits)
TS1
TS2
...
TS12
TS13
...
TS23
TS24
  • ● Framing Bit (F-bit): 1 bit per frame for synchronization
  • ● Time Slots (TS): 24 channels × 8 bits = 192 bits
  • ● Frame Rate: 8000 frames/second (125 μs period)
  • ● Channel Rate: 64 kbps per DS0 (8 bits × 8 kHz)

Line Coding: AMI & B8ZS

AMI (Alternate Mark Inversion)

  • • Binary 0: No pulse (zero voltage)
  • • Binary 1: Alternating +3V and -3V pulses
  • • Maintains zero DC component
  • • Limitation: Cannot transmit long strings of zeros (max 15 consecutive)
Data: 1 0 1 1 0 0 1 0
AMI: + 0 - + 0 0 - 0

B8ZS (Binary 8 Zero Substitution)

  • • Replaces 8 consecutive zeros with pattern: 000VB0VB
  • • V = Violation (same polarity as previous mark)
  • • B = Bipolar mark (alternates normally)
  • • Maintains synchronization while allowing clear channel
8 Zeros: 0 0 0 0 0 0 0 0
B8ZS: 0 0 0 + - 0 - +
(V=violation, B=normal mark)

Framing Formats: SF vs ESF

D4 Super Frame (SF)

  • • 12 frames grouped together
  • • Framing pattern: 100011011100 (repeats)
  • • 12 framing bits total per superframe
  • • 6th and 12th frames used for signaling (robbed-bit)
  • • Limited error detection capability
Frame bits: F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12
Pattern: 1 0 0 0 1 1 0 1 1 1 0 0

Extended Super Frame (ESF)

  • • 24 frames grouped together
  • • 24 framing bits divided into:
    • - 6 bits: Frame synchronization
    • - 6 bits: CRC-6 error check
    • - 12 bits: Data link (4 kbps channel)
  • • Pattern: 001011...001011 (repeats every 6)
  • • Advanced network management and error monitoring

3 Procedure

1

Frame Structure Analysis

Navigate to the Simulation tab. Observe the T1 frame structure showing 24 time slots. Note the framing bit position and how data is organized in bytes (8 bits per time slot). Toggle between viewing individual bits and byte values.

2

Line Coding Comparison

Switch between AMI and B8ZS line coding. Enter a data pattern with 8 consecutive zeros (e.g., "111100001111") and observe how B8ZS substitutes the pattern while AMI would violate the ones density requirement. Note the bipolar violations marked in the waveform.

3

Framing Format Analysis

Select between D4 Super Frame and Extended Super Frame formats. Observe the framing bit patterns and how they repeat over 12 or 24 frames respectively. In ESF mode, identify the CRC and data link bits.

4

Multiplexer Operation

Use the TDM Multiplexer simulation to observe how 24 DS0 channels are interleaved into a single T1 stream. Input different data patterns for each channel and verify the byte-interleaved output sequence.

Input: Ch1: 0x55, Ch2: 0xAA, Ch3: 0xFF...
Output: 0x55 (F-bit) 0xAA 0xFF ... (interleaved)
5

Bit Rate Calculations

Verify the T1 bit rate calculation: With 193 bits per frame and 8000 frames per second, the total rate is 1.544 Mbps. Calculate the effective data rate per channel (56 kbps or 64 kbps depending on signaling).

4 Interactive Simulation

Slow Fast

Try entering 8 consecutive zeros to see B8ZS substitution in action

T1 Frame Structure (193 bits)

Frame: 0 Time: 0.000 ms Active Channel: -
F-bit Data Current
Bit 0 (F) Bits 1-8 (TS1) ... Bits 185-192 (TS24)

AMI/B8ZS Waveform

Time → Polarity: +3V / 0V / -3V
Positive (+3V)
Negative (-3V)
Zero (0V)
Bipolar Violation

TDM Multiplexer (24 Channels)

Input Channels (DS0)

MUX
1.544 Mbps
Byte Interleaving
Waiting...

T1 Output Stream

Start simulation to see output...
Rate: 1.544 Mbps 0 bytes

5 Lab Report Guidelines

Required Sections

  • 1.
    Objective: State the purpose of studying T1 PDH systems and specific concepts explored.
  • 2.
    Theory: Explain T1 frame structure, AMI/B8ZS line coding, and framing formats (SF/ESF) with diagrams.
  • 3.
    Procedure: Document steps taken in the simulation, including parameter settings.
  • 4.
    Observations: Include screenshots of waveforms, frame structures, and multiplexing sequences.

Analysis Questions

Q1. Bit Rate Calculation

Calculate the exact T1 bit rate given 24 channels, 8 bits per channel, 1 framing bit, and 8000 frames/second. Show your work.

Q2. B8ZS Pattern Analysis

When transmitting eight consecutive zeros using B8ZS, what is the exact substitution pattern? Explain why this maintains synchronization.

Q3. Framing Comparison

Compare D4 Super Frame and Extended Super Frame. What are the advantages of ESF in terms of error detection and network management?

Q4. Channel Capacity

Why is the effective data rate 56 kbps per channel instead of 64 kbps when using robbed-bit signaling? Which bits are "robbed"?

Submission Checklist