Explore the Plesiochronous Digital Hierarchy through interactive simulations of frame structures, multiplexing hierarchies, and HDB3 line coding.
Upon completion of this laboratory, students will be able to:
Understand the E1 frame structure with 32 time slots, including TS0 for frame alignment and TS16 for signaling.
Analyze the multiplexing hierarchy from E1 (2 Mbps) to E5 (565 Mbps) with bit stuffing mechanisms.
Demonstrate HDB3 encoding/decoding and understand bipolar violations for clock recovery.
Comprehend plesiochronous operation and frame alignment signal (FAS) recovery mechanisms.
Calculate bit rates at different hierarchy levels and understand justification/stuffing bits.
Identify LOS (Loss of Signal), LOF (Loss of Frame), and remote alarm indications.
The E1 frame is the basic building block of the European PDH hierarchy, operating at 2.048 Mbps. It consists of 32 time slots (TS0-TS31), each carrying 8 bits, transmitted 8000 times per second (125 µs frame duration) [^2^].
Carries Frame Alignment Signal (FAS: 0011011) in odd frames and alarm indications in even frames.
Carries Channel Associated Signaling (CAS) or can be used for data in Common Channel Signaling (CCS).
30 channels carrying voice or data at 64 kbps each (PCM encoded).
PDH uses plesiochronous (nearly synchronous) multiplexing where each level combines 4 lower-order streams. Due to clock tolerances, bit stuffing (justification) is required, resulting in bit rates that are not exact multiples of 4 [^5^][^8^].
Since tributaries operate with independent clocks (plesiochronous), justification bits (R-bits) are added to accommodate rate differences. Control bits (J-bits) indicate whether R-bits carry data or are stuffing [^4^].
PDH requires full demultiplexing to access individual channels. To extract one E1 from E4 requires demultiplexing through E3 and E2 levels, creating a "multiplexer mountain" [^5^].
High Density Bipolar 3 (HDB3) is the line code used for E1 transmission. It solves the clock recovery problem of AMI (Alternate Mark Inversion) by limiting consecutive zeros to a maximum of 3 [^1^][^3^].
Binary 1s are encoded as alternating + and - pulses. Binary 0s are encoded as no pulse (0V). This ensures DC balance but fails during long zero sequences.
Replace every 4 consecutive zeros (0000) with either:
Where V = Violation (same polarity as previous pulse), B = Balancing pulse (opposite polarity).
The receiver searches for this pattern to achieve frame synchronization. Once aligned, it monitors for valid FAS in alternate frames to maintain lock [^10^].
Understand the composition of the 2.048 Mbps frame and identify overhead vs payload channels.
Explore the multiplexing process and understand bit stuffing justification.
Demonstrate HDB3 encoding and decode received waveforms.
Simulate fault conditions and observe alarm propagation.
Experiment title, student name, ID, date, and course information.
List the specific objectives as outlined in the laboratory manual.
Brief explanation of E1 frame structure, PDH hierarchy, and HDB3 coding principles (max 1 page).
Include screenshots of simulations, observed waveforms, and completed tables with measured/calculated values.
Answer specific questions, analyze bit stuffing percentages, compare AMI vs HDB3, and discuss alarm propagation.
Summarize key findings and state whether objectives were achieved.
| Criteria | Weight | Excellence Standards |
|---|---|---|
| Theory Understanding | 20% | Clear explanation of plesiochronous operation and justification |
| Simulation Results | 30% | Accurate screenshots, correct calculations, proper labeling |
| Analysis Quality | 30% | Critical thinking, comparison of coding schemes, error analysis |
| Presentation | 20% | Professional formatting, grammar, timely submission |