📡 E1-PDH Architecture Study Guide

Plesiochronous Digital Hierarchy for Communication Engineering

Undergraduate Level | ITU-T Standards G.702, G.703, G.704

1. Introduction to PDH

Definition: The Plesiochronous Digital Hierarchy (PDH) is a telecommunications transmission technology that multiplexes and transports digital data (voice and data signals) over networks using time-division multiplexing (TDM).

The PDH was developed in the 1960s and formalized through ITU-T recommendations, particularly G.702 in 1988. It represents one of the foundational technologies that revolutionized long-distance digital communication before the advent of fully synchronous systems like SDH/SONET.

The term "plesiochronous" (from Greek: plesio = near, chronos = time) describes a timing mode where signals operate at essentially the same nominal rate but allow controlled timing variations between them—typically within ±50 parts per million (ppm).

🎯 Learning Objectives

  • Understand the concept of plesiochronous operation and its significance
  • Master the E1 frame structure and time slot allocation
  • Analyze the PDH multiplexing hierarchy (E1 → E2 → E3 → E4 → E5)
  • Compare European E-carrier vs North American T-carrier systems
  • Apply bit rate calculations for various hierarchy levels
  • Identify limitations that led to SDH development

Historical Context

The CCITT (now ITU-T) initiated standardization proposals in 1972 to create a unified digital hierarchy framework. These efforts addressed the need to standardize digital transmission rates for telephony following the introduction of Pulse Code Modulation (PCM) in the 1960s.

Regional variations emerged due to existing analog telephony infrastructure:

2. Fundamental Concepts

2.1 Plesiochronous vs Synchronous Operation

🔧 Plesiochronous (PDH)

  • ✓ Each network element has independent clock
  • ✓ Nominal bit rates vary ±50 ppm
  • ✓ Bit stuffing/justification required
  • ✓ Flexible but complex demultiplexing
  • ✓ Limited network management

⚡ Synchronous (SDH)

  • ✓ All clocks trace to master reference
  • ✓ Exact frequency alignment
  • ✓ Pointer-based synchronization
  • ✓ Easy add/drop multiplexing
  • ✓ Rich overhead for management

2.2 Basic Principles

At its core, PDH employs Time-Division Multiplexing (TDM) to combine lower-bit-rate signals into progressively higher levels. Key techniques include:

Bit Stuffing (Justification): Since tributary signals operate with slightly different clock frequencies, extra bits are inserted (positive justification) or removed (negative justification) to maintain synchronization. Control bits signal the presence of stuffed bits to the receiver.

2.3 Time Slot Fundamentals

The basic building block of PDH is the 64 kbit/s channel, representing one digitized voice circuit using PCM (Pulse Code Modulation):

Sampling Rate: 8,000 samples/second (Nyquist rate for 4 kHz voice) Bits per Sample: 8 bits (A-law or μ-law compression) Channel Rate: 8,000 × 8 = 64 kbit/s

This 64 kbit/s rate forms the basis for both the European E1 (30 channels + overhead) and North American T1 (24 channels + overhead) systems.

3. E1 Frame Structure

E1 Specification: 2.048 Mbit/s line rate carrying 30 voice channels (64 kbit/s each) plus 2 overhead channels for framing and signaling.

3.1 Frame Composition

An E1 frame consists of 32 time slots of 8 bits each, transmitted at 8,000 frames per second:

E1 Frame Structure (256 bits total)
TS0
TS1
TS2
TS3
TS4
TS5
TS6
TS7
TS8
TS9
TS10
TS11
TS12
TS13
TS14
TS15
TS16
TS17
...
...
...
...
...
TS16
TS17
...
TS30
TS31
Red = Frame Alignment (TS0) Orange = Signaling (TS16) Green = Voice/Data (TS1-TS15, TS17-TS31)

3.2 Time Slot Functions

Time Slot Designation Function Bits
TS0 Frame Alignment Frame alignment signal (FAS), CRC-4, alarms 8 bits
TS1-TS15 Voice/Data Channels 15 × 64 kbit/s bearer channels 8 bits each
TS16 Signaling Channel Associated Signaling (CAS) or data 8 bits
TS17-TS31 Voice/Data Channels 15 × 64 kbit/s bearer channels 8 bits each

3.3 Frame Alignment Signal (FAS)

TS0 carries the Frame Alignment Signal to enable the receiver to identify the start of each frame:

Frame Alignment Word: 0011011 (7 bits in even frames) Bit 1: Reserved for international use Bits 2-8: Frame alignment pattern Odd Frames: Bit 2 = 1 (to avoid simulating FAS), Bits 3-8 carry alarms/flags

3.4 Multiframe Structure (CAS)

When using Channel Associated Signaling (CAS), 16 consecutive frames form a multiframe to handle signaling for all 30 channels:

16-Frame Multiframe Structure:
  • Frame 0: TS16 contains Multiframe Alignment Signal (MFAS: 0000xxxx)
  • Frames 1-15: TS16 carries signaling bits for channels 1-15 (low nibble) and 17-31 (high nibble)
  • Each channel gets 4 signaling bits (a, b, c, d) at 500 bit/s rate

3.5 Bit Rate Calculation

Frame Structure: 32 time slots × 8 bits = 256 bits/frame Frame Rate: 8,000 frames/second (125 μs frame period) Line Rate: 256 bits × 8,000 = 2,048,000 bit/s = 2.048 Mbit/s Payload Capacity: 30 channels × 64 kbit/s = 1,920 Mbit/s Overhead: 2 × 64 kbit/s = 128 kbit/s (TS0 + TS16)

4. PDH Hierarchy Levels

The E-carrier hierarchy follows a consistent quaternary (×4) multiplexing structure, with each level combining four signals from the previous level:

Level Bit Rate DS0 Channels Line Code Accuracy
E0 64 kbit/s 1 - ±100 ppm
E1 2.048 Mbit/s 30 HDB3 ±50 ppm
E2 8.448 Mbit/s 120 HDB3 ±30 ppm
E3 34.368 Mbit/s 480 HDB3 ±20 ppm
E4 139.264 Mbit/s 1,920 CMI ±15 ppm
E5 565.148 Mbit/s 7,680 CMI ±15 ppm
Important Note: The actual bit rate at each level is slightly higher than exactly ×4 due to added overhead bits for frame alignment and justification (bit stuffing).

4.1 Hierarchy Visualization

E5: 565.148 Mbit/s (7,680 channels)
↑
E4
E4
E4
E4
↑
E4: 139.264 Mbit/s (1,920 channels)
↑
E3
E3
E3
E3
↑
E3: 34.368 Mbit/s (480 channels)
↑
E2
E2
E2
E2
↑
E2: 8.448 Mbit/s (120 channels)
↑
E1
E1
E1
E1
↑
E1: 2.048 Mbit/s (30 channels)

4.2 Comparison: E-carrier vs T-carrier

Parameter European (E-carrier) North American (T-carrier)
Primary Rate E1: 2.048 Mbit/s T1: 1.544 Mbit/s
Voice Channels 30 channels 24 channels
Frame Structure 32 time slots 24 time slots + 1 framing bit
Frame Size 256 bits 193 bits
Line Code HDB3 B8ZS/AMI
Signaling TS16 (CAS) or separate Robbed-bit (SF/ESF)
Multiplexing Factor ×4 at each level ×4, ×7 (varies)

5. Multiplexing Techniques

5.1 Bit Interleaving

PDH multiplexers use bit-interleaving to combine tributary signals. Bits are taken sequentially from each input stream and combined into the higher-rate output:

Bit Interleaving Process (E1 → E2)
E1-1: Bit A1
E1-2: Bit B1
E1-3: Bit C1
E1-4: Bit D1
→
E2 Stream:
A1 B1 C1 D1 A2 B2 C2 D2...

5.2 Justification (Bit Stuffing)

Since tributaries operate plesiochronously (slightly different clock rates), justification bits are added to synchronize the streams:

Positive Justification: When a tributary is slower than the multiplexer clock, extra "stuffing" bits are inserted to prevent buffer underflow.

Negative Justification: When a tributary is faster, bits are removed (skipped) to prevent buffer overflow.

Justification Control Bits: Special overhead bits indicate whether justification bits contain valid data or are just stuffing.

5.3 E2 Frame Structure

The E2 frame multiplexes four E1 signals (2.048 Mbit/s each) into an 8.448 Mbit/s stream:

E2 Frame: 1,064 bits (1,056 information + 8 overhead) Frame Rate: 8,000 frames/second Line Rate: 1,064 × 8,000 = 8,512,000 bit/s nominal Actual Rate: 8,448,000 bit/s (accounting for justification) Justification Opportunities: Distributed throughout frame Control Bits: Indicate stuffing status for each tributary

5.4 Demultiplexing Challenge

PDH Limitation: To extract a single 64 kbit/s channel from an E4 (140 Mbit/s) stream, the signal must be fully demultiplexed through all hierarchy levels: E4 → E3 → E2 → E1 → individual channels. This "multiplexing mountain" requires expensive hardware and makes add/drop operations complex.

6. ITU-T Standards

Recommendation Title Description
G.702 Digital Hierarchy Bit Rates Defines bit rates for PDH hierarchy levels (E1-E5, T1-T5)
G.703 Physical/Electrical Characteristics Specifies interfaces, line codes (HDB3, CMI), impedance, levels
G.704 Synchronous Frame Structures Defines frame formats, alignment procedures, CRC-4
G.706 Frame Alignment and CRC Detailed procedures for frame recovery and error checking
G.823 Jitter and Wander Specifies tolerance limits for timing variations
G.921 E1 Interface Requirements Detailed E1 interface specifications

6.1 Line Codes

📊 HDB3 (High Density Bipolar 3)

Used for: E1, E2, E3 (up to 34 Mbit/s)

  • Prevents DC wander
  • Maintains clock recovery
  • Limits consecutive zeros to 3
  • Replaces 4 zeros with violation pattern (B00V or 000V)

📊 CMI (Coded Mark Inversion)

Used for: E4, E5 (139+ Mbit/s)

  • Binary '0' = 01 (low-high transition)
  • Binary '1' = 00 or 11 (alternating)
  • Simple encoding/decoding
  • Good error monitoring capability

7. Applications and Limitations

7.1 Current Applications

Despite being considered "legacy" technology, E1-PDH continues to serve critical functions:

🏭 Modern Uses of E1-PDH

  • Legacy telecommunications infrastructure and PSTN backbones
  • Cellular base station backhaul (2G/3G)
  • Industrial control systems requiring deterministic latency
  • Critical infrastructure with proven reliability requirements
  • Interim connectivity during SDH/SONET migration
  • Enterprise PBX systems and private networks

7.2 PDH Limitations

Why PDH was replaced by SDH:
  1. Complex Add/Drop: Extracting individual channels requires full demultiplexing
  2. Limited Management: No standardized overhead for network monitoring
  3. Jitter Accumulation: Cascaded multiplexers accumulate timing variations
  4. Incompatible Hierarchies: E-carrier and T-carrier require gateway equipment
  5. Scalability Ceiling: Maximum practical rate ~565 Mbit/s (E5)
  6. No Optical Standard: No standardized optical interface specification

7.3 Migration to SDH

PDH signals are mapped into SDH (Synchronous Digital Hierarchy) through a structured process:

PDH to SDH Mapping
E1 (2.048 Mbit/s)
↓
Container C-12
↓
Virtual Container VC-12 + POH
↓
Tributary Unit TU-12 + Pointer
↓
TUG-2 → TUG-3 → VC-4 → STM-1

8. Interactive Bit Rate Calculator

Calculate PDH Hierarchy Parameters

Select parameters and click Calculate...

Frame Duration Calculator

frames
Enter number of frames and click Calculate...

9. Knowledge Check

Question 1: What does "plesiochronous" mean in the context of PDH?

Question 2: How many voice channels does an E1 frame carry?

Question 3: What is the line rate of an E1 signal?

Question 4: Which line code is used for E1, E2, and E3?

Question 5: What is the main disadvantage of PDH regarding channel extraction?

10. Summary

📚 Key Takeaways

  • E1-PDH is a plesiochronous TDM system operating at 2.048 Mbit/s with 30 voice channels
  • Frame structure: 32 time slots × 8 bits, transmitted at 8,000 frames/second
  • Hierarchy builds by multiplexing 4 signals at each level (E1→E2→E3→E4→E5)
  • Bit stuffing (justification) compensates for clock variations between tributaries
  • HDB3 line code ensures DC balance and clock recovery for rates up to 34 Mbit/s
  • Main limitation: Complex add/drop requiring full demultiplexing, leading to SDH development
  • ITU-T standards G.702, G.703, and G.704 define the complete E1 interface specification
Further Study: After mastering E1-PDH, proceed to study SDH/SONET architecture to understand how modern synchronous networks overcome PDH limitations while maintaining backward compatibility with E1 tributaries.